Commandant
New member
Hi everyone,
I installed a brand new Furuno radar, a DRS4D NXT, on my vessel.
When powering up the radar it doesn't come up on the network.
I've created a test setup now in my garage with a PC, network switch and two RJ45 cables to try to find the problem.
The 10Mbps LED, nor the 100Mbps LED on the network switch show any activity.
Upon opening the dome and checking the PCB inside, I noticed the 12V and 5V LEDs are turning ON and remain ON, but the FPGA Check1 LED keeps blinking while the CPU Check1 LED remains OFF.
I'm starting to think the radar cannot get passed its boot procedure and therefore remains in some booting state as long as it cannot pass the FPGA Check1 status.
The 'ether speed' and 'ether link' LEDs remain OFF all the time, but I guess that's because the radar can't get passed the FPGA and CPU check. Hereunder the pics for clarification: (The picture was taken just when the FPGA Check1 LED blinked ON, so don't assume the FPGA Check1 has completed).
My question now is: What can I do to get the radar passed the FPGA Check1 and CPU Check1 ?
I installed a brand new Furuno radar, a DRS4D NXT, on my vessel.
When powering up the radar it doesn't come up on the network.
I've created a test setup now in my garage with a PC, network switch and two RJ45 cables to try to find the problem.
The 10Mbps LED, nor the 100Mbps LED on the network switch show any activity.
Upon opening the dome and checking the PCB inside, I noticed the 12V and 5V LEDs are turning ON and remain ON, but the FPGA Check1 LED keeps blinking while the CPU Check1 LED remains OFF.
I'm starting to think the radar cannot get passed its boot procedure and therefore remains in some booting state as long as it cannot pass the FPGA Check1 status.
The 'ether speed' and 'ether link' LEDs remain OFF all the time, but I guess that's because the radar can't get passed the FPGA and CPU check. Hereunder the pics for clarification: (The picture was taken just when the FPGA Check1 LED blinked ON, so don't assume the FPGA Check1 has completed).
My question now is: What can I do to get the radar passed the FPGA Check1 and CPU Check1 ?